The present invention relates to a semiconductor device fabricating method and, more particularly, to a semiconductor device fabricating method for fabricating a semiconductor device of a multilayer wiring construction.
The recent progressive miniaturization of LSI devices (large-scale integrated devices) has increased the importance of the dimensional reduction of repetitive patterns, such as patterns of memory cells. Therefore, pattern size must be reduced securing a margin for absorbing an error in the register of superposed patterns to allow misalignment between the superposed patterns in addition to the reduction of line width, space width and the diameter of contacts by using exposure light of a short wavelength for lithographic processes.
A related art method of fabricating a SRAM (static random-access memory) will be described with reference to FIG. 1 showing a memory cell of a SRAM of a 0.35 .mu.m minimum feature length.
An element isolation oxide film 32 of, for example, a LOCOS (local oxidation of silicon) structure is formed in a pattern on a major surface of a Si (silicon) wafer 31. A gate oxide film 33 is formed on the Si wafer 31 so as to cover element active regions surrounded by the element isolation oxide film 32. Then, a polycide layer, i.e., a laminated layer consisting of a polysilicon layer and a metal silicide layer having a high melting point, serving as a first wiring layer 34 including a gate electrode for a MOS transistor is formed on the gate oxide film 33.
Subsequently, lightly doped regions, not shown, for forming an LDD (lightly doped drain) structure are formed in regions of the surface of the Si wafer 31 on the opposite sides of the first wiring layer 34. Then, side walls 35 of SiO.sub.2 are formed on the side surfaces of the first wiring layer 34, and then heavily doped regions which serve as the source and the drain of a MOS transistor are formed.
Then, a first layer insulating film 36 of SiO.sub.2 is formed over the entire surface of the Si wafer 31. The first layer insulating film 36 of SiO.sub.2 is subjected to selective etching to form a first viahole reaching a heavily doped region forming a ground line or a heavily doped region forming the source or the drain of the MOS transistor. Then, a second wiring layer 39 of a polycide is formed on the first layer insulating film 36 of SiO.sub.2 and the second wiring layer 39 is connected through the first viahole to the heavily doped region serving as a ground line and the heavily doped region serving as the source or the drain of the MOS transistor.
Then, a second layer insulating film 40 of SiO.sub.2 is formed over the entire surface of the Si wafer 31. The first layer insulating film 36 of SiO.sub.2 and the second layer insulating film 40 of SiO.sub.2 are subjected to selective etching to form a second viahole for connecting a high-resistance element included in the flip-flop of the SRAM and a heavily doped region serving as a storage node. Then, a third wiring layer 42 including a high-resistance element is formed on the second layer insulating film 40 of SiO.sub.2 and the third wiring layer 42 is connected through the second viahole to the heavily doped region serving as a storage node. Subsequently, a third layer insulating film 43 of SiO.sub.2 is formed over the entire surface of the silicon wafer 31, and a first Si.sub.3 N.sub.4 film 44 for keeping the high-resistance element away from moisture is formed on the third layer insulating film 43 of SiO.sub.2.
Then, a fourth layer insulating film 45 of SiO.sub.2 is formed over the entire surface of the Si wafer 31 and the fourth layer insulating film 45 is subjected to a flattening process. Then, the fourth layer insulating film 45 of SiO.sub.2, the first Si.sub.3 N.sub.4 film 44, the third layer insulating film 43 of SiO.sub.2 and the second layer insulating film 40 of SiO.sub.2 are etched selectively to form a third viahole for connecting the second wiring layer 39 and the bit line to expose a portion of the second wiring layer 39 in the third viahole. A tungsten plug 48 is formed in the third viahole so as to be connected to the second wiring layer 39. Subsequently, a fourth wiring layer 49 forming a bit line is formed on the fourth layer insulating film 45 of SiO2 so as to be connected to the tungsten plug 48. Finally, an overcoating film 50 is formed over the entire surface of the Si wafer 31.
When forming the third viahole in the fourth layer insulating film 45 of SiO.sub.2, the first Si.sub.3 N.sub.4 film 44, the third layer insulating film 43 of SiO.sub.2 and the second layer insulating film 40 of SiO.sub.2 formed over the second wiring layer 39 by lithographic techniques by this related art method of fabricating a SRAM, it is possible that the pattern is dislocated relative to the second wiring layer 39 because of the limited pattern registering accuracy of a stepper employed for exposure. Therefore, a portion of the first layer insulating film 36 of SiO.sub.2 underlying the second layer insulating film 40 of SiO.sub.2 is etched in addition to the foregoing films including the second layer insulating film 40 of SiO.sub.2. Consequently, the third viahole penetrates the second wiring layer 39 and reaches the first wiring layer 34 serving as the gate electrode and underlying the second wiring layer 39, and the second wiring layer 39 and the first wiring layer 34 are connected electrically by the tungsten plug 48 formed in the third viahole. Therefore, the lines of the second wiring layer 39 must be formed in a width having a margin to absorb an error in aligning the third viahole with the second wiring layer 39, which imposes a restriction on the miniaturization of the memory cell.